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| CXD2510Q CD Digital Signal Processor Description The CXD2510Q is a digital signal processor LSI for CD players and is equipped with the following functions. * Wide frame jitter margin (28 frames) due to a builtin 32K RAM * Bit clock, which strobes the EFM signal, is generated by the digital PLL * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction * Quadruple-speed, double-speed and variable pitch playback * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and Sub Q data error correction * Digital spindle servo (built-in oversampling filter) * 16-bit traverse counter * Asymmetry compensation circuit * Serial bus-based CPU interface * Error correction monitor signals are output from a new CPU interface. * Servo auto sequencer * Fine search which performs high-precision track jumps * Digital audio interface output * Digital level meter, peak meter * Bilingual compatible Features * All digital signals processed with a single chip during playback * High-integrated mounting possible due to a built-in RAM Structure Silicon gate CMOS IC Absolute Maximum Ratings VDD * Supply voltage -0.3 to +7.0 V * Input voltage VI -0.3 to +7.0 V (VSS - 0.3V to VDD + 0.3V) * Output voltage VO -0.3 to +7.0 V * Storage temperature Tstg -40 to +125 C * Supply voltage difference Vss - AVss -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V -L01 80 pin QFP (Plastic) -L051 Recommended Operating Conditions 4.50 to 5.50 V * Supply voltage VDD * Operating temperature Topr -20 to +75 C The VDD (min.) for the CXD2510Q varies according to the playback speed and built-in VCO selection. The VDD (min.) is 4.50 V when high speed VCO and quadruple-speed playback are selected (variable pitch off). The VDD (min.) for the CXD2510Q under various conditions are as shown in the following table. VDD (min.) [V] Playback speed VCO high-speed VCO normal-speed x4 x 21 x2 x1 x 12 4.50 4.00 3.40 3.40 3.40 -- -- 4.00 3.40 3.40 Dashes indicate that there is no assurance of the processor operating. All values are for variable pitch off. 1 When the internal operation of the LSI is set to normal-speed playback and the operating clock of the signal processor is doubled, double-speed playback results. 2 When the internal operation of the LSI is set to double-speed mode and the crystal oscillating frequency is halved in low power consumption mode, normal-speed playback results. Input/output Capacitances * Input capacitance CI * Output capacitance CO Note) Measurement conditions 12 (max.) pF 12 (max.) pF for high impedance VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E94412A11 CXD2510Q Block Diagram FSTT XTAO XTSL XTAI VCKI VPCO 56 53 54 55 17 16 23 AVDD FSOF 57 C16M 58 PDO 11 VCOI VCOO Clock generator 21 AVSS 32K RAM 33 VDD 73 VDD Register 9 8 FILI 19 FILO 18 CLTV 22 RF 24 ASYI 26 ASYO 27 ASYE 28 WFCK 62 SCOR 63 EXCK 65 SBSO 64 EMPH 61 SQCK 67 SQSO 66 MON FSW MDP MDS 3 2 4 5 Noise shaper 4 25 13 70 6 50 51 32 31 18-times ever sampling filter Timing generator 2 CLV processor Subcode Q processor Subcode P-W processor Error corrector Timing generator 1 MIX Sync protector 8 D/A data processor Serial/parallel processor PCO 20 Digital PLL vari-pitch double speed 12 Address generator Priority encoder 52 VSS VSS EFM demodulator 30 PSSL DA01 to 16 16 68 MUTE Peak detector Digital out 60 DOUT 59 MD2 71 DATA CPU interface 74 CLOK 72 XLAT TEST 10 NC Servo auto sequencer 77 DATO 79 CLKO 78 XLTO 75 69 80 76 1 TEST0 APTL WDCK XRST LOCK LRCK SENS BIAS APTR MIRR CNIN SEIN FOK Asymmetry correction. WFCK SCOR EMPH DOUT SBSO FSOF XTAO FSTT XTSL MD2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 EXCK SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOK SEIN CNIN DATO XLTO CLKO MIRR 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DA10 DA11 DA12 DA13 DA14 DA15 DA16 VDD LRCK WDCK PSSL NC ASYE ASYO ASYI BIAS TEST0 APTL DA01 DA02 XTAI DA03 VSS DA04 DA05 DA06 CLTV DA07 LOCK MDP MDS VCOO VPCO VCOI VCKI AVDD FOK PDO FILO PCO FILI AVSS VSS DA08 TEST MON FSW NC -2- NC NC RF DA09 Pin Configuration C16M APTR CXD2510Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol FOK FSW MON MDP MDS LOCK NC VCOO VCOI TEST PDO Vss TEST0 NC NC VPCO VCKI FILO FILI PCO AVss CLTV AVDD RF BIAS ASYI ASYO ASYE NC PSSL WDCK LRCK VDD I O O 1, 0 1, 0 I I I O I -- Audio data output mode switching input. Low: serial output; high: parallel output. D/A interface for 48-bit slot. Word clock f = 2Fs. D/A interface for 48-bit slot. LR clock f = Fs. Power supply (5V). 1, 0 I O I O I O 1, Z, 0 Analog -- -- -- 1, Z, 0 Variable pitch PLL charge pump output. Variable pitch clock input from the external VCO. fc center = 16.9344MHz. Master PLL filter output. Master PLL filter input. Master PLL charge pump output. Analog GND. Master VCO control voltage input. Analog power supply (5V). EFM signal input. Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = Vss, high = VDD). Low: asymmetry circuit off; high: asymmetry circuit on O I I O 1, Z, 0 I O O O O O Z, 0 1, 0 1, Z, 0 1, Z, 0 1, 0 -- 1, 0 Analog EFM PLL oscillation circuit output. Analog EFM PLL oscillation circuit input. fLOCK = 8.6436MHz. TEST pin. Normally GND. Analog EFM PLL charge pump output. GND TEST output pin. Normally open. I/O Description Focus OK input. Used for SENS output and the servo auto sequencer. Spindle motor output filter switching output. Spindle motor on/off control output. Spindle motor servo control. Spindle motor servo control. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. -3- CXD2510Q Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Symbol DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 APTR APTL Vss XTAI XTAO XTSL FSTT FSOF C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK I O I O O O I O O O O O I O O O O O O O O O O O O O O O O O O I/O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Description DA16 (MSB) output when PSSL = 1. 48-bit slot serial data (two's complement, MSB first) when PSSL = 0. DA15 output when PSSL = 1. 48-bit slot bit clock when PSSL = 0. DA14 output when PSSL = 1. 64-bit slot serial data (two's complement, LSB first) when PSSL = 0. DA13 output when PSSL = 1. DA12 output when PSSL = 1. DA11 output when PSSL = 1. DA10 output when PSSL = 1. DA09 output when PSSL = 1. DA08 output when PSSL = 1. DA07 output when PSSL = 1. DA06 output when PSSL = 1. DA05 output when PSSL = 1. DA04 output when PSSL = 1. DA03 output when PSSL = 1. DA02 output when PSSL = 1. DA01 output when PSSL = 1. 64-bit slot bit clock when PSSL = 0. 64-bit slot LR clock when PSSL = 0. GTOP output when PSSL = 0. XUGF output when PSSL = 0. XPLCK output when PSSL = 0. GFS output when PSSL = 0. RFCK output when PSSL = 0. C2PO output when PSSL = 0. XRAOF output when PSSL = 0. MNT3 output when PSSL = 0. MNT2 output when PSSL = 0. MNT1 output when PSSL = 0. MNT0 output when PSSL = 0. Aperture compensation control output. This pin outputs a high signal when the right channel is used. Aperture compensation control output. This pin outputs a high signal when the left channel is used. GND 16.9344MHz crystal oscillation circuit input. Also the 33.8688MHz input. 1, 0 16.9344MHz crystal oscillation circuit output. Crystal selector input. The crystal is low for 16.9344MHz, and high for 33.8688MHz. 1, 0 1, 0 1, 0 2/3 frequency divider output for Pins 53 and 54. This pin does not change with the variable pitch. 1/4 frequency divider output for Pins 53 and 54. This pin does not change with the variable pitch. 16.9344MHz output. This pin changes simultaneously with the variable pitch. Digital-out on/off control. High: on; low: off 1, 0 1, 0 1, 0 1, 0 1, 0 Digital-out output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. WFCK (write frame clock) output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. -4- CXD2510Q Pin No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOK SEIN CNIN DATO XLTO CLKO MIRR I I I O O O I O I I -- I I I I/O 1, 0 Description Sub Q 80-bit and PCM peak and level data 16-bit output. SQSO readout clock input. High: mute; low: release 1, Z, 0 SENS output to CPU. System reset. Reset when low. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Power supply (5V). Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input. 1, 0 1, 0 1, 0 Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Mirror signal input. Notes) * The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window open.) * XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * GFS goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136. * C2PO represents the data error status. * XRAOF is generated when the 32K RAM exceeds the 28F jitter margin. -5- CXD2510Q Electrical Characteristics DC Characteristics Item Input voltage (1) Input voltage (2) Input voltage (3) Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Low level output voltage High level output voltage Low level output voltage (VDD = AVDD = 5.0V 10%, Vss = AVss = 0V, Topr = -20 to +75C) Conditions VIH (1) VIL (1) VIH (2) VIL (2) VIN (3) Schmitt input Analog input 0.8VDD 0.2VDD Vss VDD - 0.5 0 VDD - 0.5 0 0 VDD VDD 0.4 VDD 0.4 0.4 VDD 0.4 5 5 Min. 0.7VDD 0.3VDD Typ. Max. Unit V V V V V V V V V V V V A A 1, 2, 3 8 6 7 5 3 4 2 Applicable pins 1 VOH (1) IOH = -1mA VOL (1) IOL = 1mA VOH (2) IOH = -1mA VOL (2) IOL = 2mA VOL (3) IOL = 2mA VOH (4) IOH = -0.28mA VDD - 0.5 VOL (4) IOL = 0.36mA ILI ILO VI = 0 to 5.50V VO = 0 to 5.50V 0 -5 -5 Input leak current Tri-state pin output leak current Applicable pins 1 XTSL, DATA, XLAT, MD2, PSSL 2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE 3 CLTV, FILI, RF 4 MDP, PDO, PCO, VPCO 5 ASYO, DOUT, FSTT, FSOF, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK 6 FSW 7 FILO 8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO -6- CXD2510Q AC Characteristics 1. XTAI pin, VCOI pin (1) When using self-oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (2) When inputting pulses to XTAI and VCOI (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTAI VDD/2 VIHX x 0.1 VILX tR tF (3) When inputting sine waves to XTAI and VCOI pins via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 10%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. VDD+0.3 Unit Vp-p -7- CXD2510Q 2. CLOK, DATA, XLAT, CNIN, SQCK EXCK pins (VDD = AVDD = 5.0V 10%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750 65 7.5 Unit MHz ns ns ns ns ns MHz ns kHz s tWCK tSU tH tD tWL fT EXCK SQCK pulse width tWT CNIN freqency fT CNIN pulse width tWT When $44 and $45 are excuted. 1/fCK tWCK CLOK tWCK DATA XLAT EXCK CNIN SQCK tSU tH tD tWL tWT 1/fT tWT SBSO SQSO tSU tH Description of Functions 1. CPU Interface and Instructions * CPU interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D1 D2 D3 D0 D1 D2 D3 750ns or more Data XLAT Address Registers 4 to E Valid 300ns max * Information on each address and the data is provided in Table 1-1. * The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. -8- Command Table Data 1 Data 2 Data 3 D0 D2 D0 D1 -- 0 -- -- D3 D2 0 0 D1 D3 D0 -- D0 D3 D1 D2 Data 4 D0 D3 D2 D1 AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 Register name Command D1 0 Address D3 D2 4 Auto sequence 0 1 5 TR0 Blind (A, E), Overflow (C, G) 0 TR3 TR2 TR1 -- 1 -- -- -- -- -- -- -- -- 0 1 -- -- -- Brake (B) 1 -- -- 0 SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0 -- -- -- -- -- -- 6 Sled_kick, brake (D) Kick (F) 1 1 32,76816,384 8,192 4,096 2,048 1,024 512 256 64 128 32 16 0 1 7 Auto sequence (N) track jump count setting 0 0 0 CDROM DOUT D.out WSEL Mute Mute-F 0 1 8 4 2 1 8 -- MODE specification 1 0 VCO ASHS SOCT SEL BiliGL FLFC MAIN SUB 0 0 0 -- -- -- -- -- -- -- -- -9- 0 1 DCLV DSPB ASEQ DPLL BiliGL ON-OFF ON-OFF ON-OFF ON-OFF 9 Function specification 1 0 -- -- -- -- -- -- -- A 1 0 Audio CTRL 1 0 Vari Vari Mute ATT PCT1 PCT2 Up Down 32,76816,384 8,192 4,096 2,048 1,024 512 -- -- -- -- -- -- -- -- B 1 1 Traverse monitor counter setting 0 0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 1 0 256 128 64 32 16 8 4 2 1 C Spindle servo coefficient setting 0 1 DCLV PWM MD 1 1 0 Gain DCLV0 0 0 -- -- -- -- -- -- -- -- D TB TP CLV CTRL 1 1 Gain CLVS -- -- -- -- -- -- -- -- -- -- -- -- E 1 0 CLV mode 1 1 CM3 CM2 CM1 CM0 -- Table 1-1. -- -- -- -- -- -- -- -- -- -- -- CXD2510Q Reset Initialization Data 1 Data 2 Data 3 D0 D2 D3 -- -- -- D2 D1 -- -- -- D1 D0 0 0 D3 D0 -- D0 0 0 0 0 D3 D2 D1 Data 4 D0 D3 D1 0 0 0 D2 0 Register name Command D1 0 Address D3 D2 4 Auto sequence 0 1 5 -- Blind (A, E), Overflow (C, G) 0 0 1 0 1 1 -- -- -- -- -- -- -- -- Brake (B) 1 0 1 1 1 0 0 0 0 0 -- -- -- -- 0 1 -- -- -- 6 Sled_kick, brake (D) Kick (F) 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 -- -- -- -- 7 Auto sequence (N) track jump count setting 0 0 0 0 0 0 0 0 0 0 -- -- 0 1 0 0 0 0 8 MODE specification 1 0 -- -- -- -- -- -- - 10 - 0 1 0 0 1 1 0 0 0 0 -- 1 0 0 1 1 0 0 0 0 0 -- 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 -- 0 0 0 0 1 0 -- -- -- -- -- 1 0 0 0 0 0 -- -- -- -- -- Table 1-2. 9 Function specification 1 0 -- -- -- -- -- -- -- A Audio CTRL 1 0 -- -- -- -- -- -- -- B Traverse monitor counter setting 1 0 0 0 0 0 0 0 0 C Servo coefficient setting 1 1 -- -- -- -- -- -- -- D CLV CTRL 1 1 -- -- -- -- -- -- -- E CLV mode 1 1 -- -- -- -- -- -- -- CXD2510Q CXD2510Q The meaning of the data for each address is explained below. $4X commands Register name Data 1 Command AS3 AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 4 Command Cancel FineSearch Focus-On 1 TrackJump 10 TrackJump 2N TrackJump AS3 0 0 0 1 1 1 AS2 0 1 1 0 0 1 AS1 0 0 1 0 1 0 AS0 0 RXF 1 RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the TRACK JUMP commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. Max. timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To invalidate the MAX timer, set the MAX timer value to 0. $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) $6X commands Register name 6 SD3 Data 1 KICK (D) SD2 SD1 SD0 KF3 Data 2 KICK (F) KF2 KF1 KF0 TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) SD3 23.2ms 11.6ms KF3 0.72ms SD2 11.6ms 5.8ms KF2 0.36ms - 11 - SD1 5.8ms 2.9ms KF1 0.18ms SD0 2.9ms 1.45ms KF0 0.09ms CXD2510Q $7X commands Auto sequence track jump count setting Command Auto sequencer track jump count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N track jump is executed, and the jump count setting when fine search is executed for auto sequence. * The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. * When N is from 0 to 15, the number of 2N track jumps is counted according to the signals input from the CNIN pin. When N is 16 or over, it is counted according to the signals input from the MIRR pin. $8X commands Command MODE specification Data 1 D3 CDROM D2 DOUT Mute D1 D.out Mute-F D0 D3 D2 ASHS Data 2 D1 SOCT D0 0 WSEL VCO SEL Command bit CDROM = 1 CDROM = 0 C2PO timing See the Timing Chart 1-3 See the Timing Chart 1-3 Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing When Digital out is on (MD2 pin = 1), DOUT output is muted. When Digital out is on, DOUT output is not muted. Command bit D. out Mute F = 1 D. out Mute F = 0 Processing When Digital out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital out is either on or off. - 12 - CXD2510Q MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DOUT Mute D.out Mute F DOUT output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -dB 0dB off DA output 0dB -dB 0dB -dB 0dB -dB See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit VCOSEL = 0 VCOSEL = 1 Processing The built-in VCO is set to normal-speed. The built-in VCO is set to high-speed. Use Used for normal-speed and double-speed (double correction) playback. Used for quadruple-speed and double-speed (quadruple correction) playback. Command bit ASHS = 0 ASHS = 1 Function Use The command transfer rate to SSP is set Used for normal-speed and double-speed to normal-speed. (double correction) playback. The command transfer rate to SSP is set Used for quadruple-speed and double-speed to half-speed. (quadruple correction) playback. Command bit SOCT = 0 SOCT = 1 Sub Q is output from the SQSO pin. Function Each output signal is output from the SQSO pin. Input the readout clock to SQCK. (See the Timing Chart 2-4.) - 13 - CXD2510Q $9X commands Command Data 1 D3 D2 D1 D0 D3 BiliGL MAIN D2 BiliGL SUB Data 2 D1 FLFC D0 0 Function DCLV DSPB A.SEQ D.PLL specifications ON-OFF ON-OFF ON-OFF ON-OFF Command bit CLV mode During CLVS mode During CLVP mode Contents FSW = low, MON = high, MDS = Z; MDP = servo control signal, carrier frequency of 230Hz at TB = 0, and 460Hz at TB = 1. FSW = Z, MON = high; MDS = speed control signal, carrier frequency of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz. MDS = PWM polarity signal, carrier frequency of When DCLV 132kHz. PWM and MD = 1 MDP = PWM absolute value output (binary), carrier frequency of 132kHz. MDS = Z When DCLV MDP = ternary PWM output, carrier frequency PWM and MD = 0 of 132kHz. DCLV on/off = 0 DCLV on/off = 1 (FSW, MON not required) During CLVS and CLVP modes When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches simultaneously with the CLVP/CLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1. Command bit DSPB = 0 DSPB = 1 FLFC is normally 0. Processing Normal-speed playback, C2 error correction quadruple correction, variable pitch possible. Double-speed playback, C2 error correction double correction, variable pitch prohibited. - 14 - CXD2510Q SENS output Microcomputer serial register value (latching not required) $0X $1X $2X $3X $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX Description of SENS signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the played back frame sync is obtained with the correct timing. Measures the number of tracks set with Reg B. High when Reg B is latched, low when the initial Reg B number is input by CNIN. Measures the number of tracks set with Reg B. High when Reg B is latched, toggles each time the Reg B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg B number. Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. Meaning ASEQ = 0 Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 SEIN (FZC) SEIN (A.S) SEIN (T.Z.C) SEIN (SSTOP) XBUSY FOK SEIN (Z) GFS COMP COUT OV64 0 COUT OV64 Command bit DPLL = 0 DPLL = 1 Meaning RFPLL is analog. PDO, VCOI and VCOO are used. RFPLL is digital. PDO is impedance. External parts for Pins 18 to 20 are required even when analog PLL is selected. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO: The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. - 15 - CXD2510Q $AX commands Command Audio CTRL Data 1 D3 Vari Up D2 Vari Down D1 Mute D0 ATT D3 PCT1 D2 PCT2 Data 2 D1 0 D0 0 Vari Up Vari Down Pitch XTal 0% VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0% -0.1% -0.2% XTal 0% Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off. -12dB Mute conditions (1) When register A mute = 1. (2) When MUTE pin = 1. (3) When register 8 D.out mute = 1 and the Digital out is on (MD2 pin = 1). (4) When GFS stays low for over 35ms (at normal speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain x 0dB x 0dB Mute x 0dB ECC correction ability C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Description of level meter mode (see the Timing Chart 1-4.) * When this LSI is set to this mode, it can possess digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits of data are Sub Q data (see 2. Subcode Interface). The last 16 bits are LSB first 15-bit PCM data (absolute values). The final bit is PCM data. However, it is high when generated by the left channel and low when generated by the right channel. * PCM data is reset and the L/R flag is reversed after one readout. The maximum value for this status is then measured until the next readout. - 16 - CXD2510Q Description of peak meter mode (see the Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the LSI internal register is reset. In other words, the PCM maximum value detection register is not reset by the readout. * To reset the PCM maximum value register, set PCT1 = PCT2 = 0 or set the $AX mute. * The Sub Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Relative time operates as normal. * The final bit (L/R flag) of the 96-bit data is normally 0. * The pre-value hold and average value interpolation data are fixed to level (-) for this mode. $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set when the traverse status is monitored by the SENS output COMP and COUT. $CX commands Command D3 Data 1 D2 D1 D0 D3 0 Data 2 D2 Gain DCLV0 D1 0 D0 0 Explanation Valid only when DCLV = 1. Valid when DCLV = 1 or 0. Servo coefficient Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 setting CLV CTRL ($DX) Gain CLVS The spindle servo gain is externally set when DCLV = 1. * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB Note) When DCLV = 0, the CLVS gain is as follows. When Gain CLVS = 0, GCLVS = -12dB. When Gain CLVS = 1, GCLVS = 0dB. - 17 - CXD2510Q * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV0 0 1 GDCLV 0dB +6dB $DX commands Command CLV CTRL D3 DCLV PWM MD D2 TB D1 TP D0 Gain CLVS See the $CX commands Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Command bit TB = 0 TB = 1 TP = 0 TP = 1 Explanation (See the Timing Chart 1-6.) Digital CLV PWM mode specified. Both MDS and MDP are used. Digital CLV PWM mode specified. Ternary MDP values are output. Explanation Bottom hold in CLVS and CLVH modes at a cycle of RFCK/32. Bottom hold in CLVS and CLVH modes at a cycle of RFCK/16. Peak hold in CLVS mode at a cycle of RFCK/4. Peak hold in CLVS mode at a cycle of RFCK/2. Note) Peak hold is performed at 34kHz in CLVH mode. - 18 - CXD2510Q $EX commands Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 CM0 CM3 0 1 1 1 1 1 0 STOP KICK BRAKE CLVS CLVP CLVA CM2 0 0 0 1 1 1 1 CM1 0 0 1 1 0 1 1 CM0 0 0 0 0 0 1 0 Mode STOP KICK BRAKE CLVS CLVH CLVP CLVA Explanation See the Timing Chart 1-7. See the Timing Chart 1-8. See the Timing Chart 1-9. : Spindle motor stop mode. : Spindle motor forward rotation mode. : Spindle motor reverse rotation mode. : Rough servo mode. When the RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the RF-PLL capture range. : PLL servo mode. : Automatic CLVS/CLVP switching mode. This mode is normally used during playback. - 19 - Timing Chart 1-3 LRCK 48 bit slot WDCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG - 20 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD2510Q Timing Chart 1-4 750ns to 120s 80 81 96 1 2 3 SQCK SQSO CRCF D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R Sub Q Data See "Sub Code Interface" 15-bit peak-data Absolute value display, LSB first Peak data L/R flag - 21 - 2 3 1 2 3 96 clock pulses CRCF R/L Peak data of this section 16 bit 1 WFCK 96 clock pulses SQCK SQSO L/R CRCF 96 bit data Hold section Level Meter Timing CXD2510Q Timing Chart 1-5 1 1 2 3 2 3 WFCK 96 clock pulses 96 clock pulses SQCK - 22 - CRCF Measurement CRCF CRCF Measurement Measurement Peak Meter Timing CXD2510Q CXD2510Q Timing Chart 1-6 DCLV PWM MD = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP Z 132kHz 7.6s DCLV PWM MD = 1 MDS Deceleration Acceleration MDP Deceleration 7.6s n * 236 (ns) n=0 to 31 Output Waveforms with DCLV = 1 Timing Chart 1-7 DCLV = 0 STOP MDS Z MDP L FSW L MON L DCLV = 1 DCLV PWM MD = 0 STOP MDS Z MDP Z FSW and MON are the same as for DCLV = 0 - 23 - CXD2510Q DCLV = 1 DCLV PWM MD = 1 STOP MDS MDP L FSW and MON are the same as for DCLV = 0 Timing Chart 1-8 DCLV = 0 KICK MDS Z MDP H FSW L MON H DCLV = 1 DCLV PWM MD = 0 KICK MDS Z MDP H Z 7.6s FSW and MON are the same as for DCLV = 0 DCLV = 1 DCLV PWM MD = 1 KICK MDS H MDP H L FSW and MON are the same as for DCLV = 0 - 24 - CXD2510Q Timing Chart 1-9 DCLV = 0 BRAKE MDS Z MDP L FSW L MON H DCLV = 1 DCLV PWM MD = 0 BRAKE MDS Z MDP L Z FSW and MON are the same as for DCLV = 0 DCLV =1 DCLV PWM MD = 1 MDS L MDP H L FSW and MON are the same as for DCLV = 0 - 25 - CXD2510Q 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK. Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame. This is accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from the SQSO pin. 2-1. P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-1.) 2-2. 80-bit Sub Q read Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * In the CXD2510Q, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. * Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In this LSI, the SQCK input is detected, and the retriggerable monostable multivibrator is reset during low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration that SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others. * In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit P/S register. Input and output for ring control 1 are shorted in peak meter or level meter mode. Ring control 2 is shorted in peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. * In addition, as previously mentioned, the absolute time after peak is generated is stored in the memory in peak meter mode. Fig. 2-3 shows the Timing Chart. * Although a clock is input from the SQCK pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120s. - 26 - CXD2510Q Timing Chart 2-1 Internal PLL clock 4.3218 DMHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 27 - Block Diagram 2-2 (ASEC) (AMIN) ADDRS CTRL (AFRAM) SUBQ SIN 80 bit S/P Register ABCD EFGH 8 Order Inversion 8 8 8 8 8 8 8 8 HGFEDCBA 80 bit P/S Register SO SI LD LD LD LD LD LD LD SUBQ LD - 28 - CRCC Monostable multivibrator SHIFT LOAD CONTROL SO 16 bit P/S register SI 16 Peak detection ABS time load control for peak value SHIFT SQCK Ring control 1 Ring control 2 CRCF Mix SQSO CXD2510Q Timing Chart 2-3 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK SCOR Determined by mode CRCF1 80 or 96 Clock CRCF2 SQSO CRCF1 SQCK Register load forbidder - 29 - 270 to 400s when SQCK = high. 750ns to 120s ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Monostable Multivibrator (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2510Q Timing Chart 2-4 Example: $802 latch Set SQCK and EXCK high during this interval. XLAT 750ns or more Internal signal latch SQCK SQSO C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 Signal Explanation PER0 to PER7 RF jitter amount (used to adjust the focus bias). 8bit binary data in PER0 = LSB, PER7 = MSB. FOK Focus OK GFS High when the frame sync and the insertion protection timing match. - 30 - Description ; C1 pointer reset ; C1 pointer reset C2F2 0 0 0 0 ; C1 pointer set ; C1 pointer set 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 -- -- LOCK GFS is sampled at 460 Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. EMPH Outputs a high signal when the playback disc has emphasis. RF jitter amount, PER0 to PER7 is output in binary code.When RF jitter amount is little, value of binary code is small. Description No C2 errors One C2 error corrected Two C2 errors corrected ; C2 pointer set ; C2 pointer reset ; C2 pointer reset Three C2 errors corrected ; C2 pointer reset Four C2 errors corrected ; C2 pointer reset -- C2 correction impossible ; C1 pointer copy C2 correction impossible ; C2 pointer set C1F2 C1F1 C1F0 0 0 0 No C1 errors 0 0 1 One C1 error corrected 0 1 0 0 1 1 1 0 0 No C1 errors 1 0 1 One C1 error corrected 1 1 0 Two C1 errors corrected ; C1 pointer set CXD2510Q 1 1 1 C1 correction impossible ; C1 pointer set CXD2510Q 3. Description of Other Functions 3-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 3-1. The CXD2510Q has a built-in three-stage PLL. * The first-stage PLL regenerates the variable pitch. LPF and VCO are necessary as external parts. The minimum variable amount of the pitch is 0.1%. The output of this first-stage PLL is used as a reference for all clocks within the LSI. Input the XTAO output to the VCKI pin when variable pitch is not used. * The second-stage PLL regenerates a high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock, and has a 150kHz (normal state) or more capture range. * The digital PLL has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off . * High-frequency components such as 3T and 4T may contain deviations. In such a case, turning the secondary loop off yields better playability. However, in this case the capture range becomes 50kHz. - 31 - CXD2510Q Block Diagram 3-1 OSC X'Tal 16.9344MHz (384Fs) Phase comparator 1/4 1/1000 XTSL LPF VPCO 1/4 1/1000 + n VCO 19.78 to 13.26MHz VCKI 2/1 MUX Vari-Pitch Up down counter n = -217 to 168 Microcomputer control Vari-Pitch Phase comparator I/M PCO I/N FILI FILO CLTV VCO Digital PLL VDD RFPLL CXD2510Q - 32 - CXD2510Q 3-2. Frame Sync Protection * In a CD player operating at normal speed, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2510Q, window protection and forward protection/backward protection have been adopted for frame sync protection. The adoption of these functions achieves very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. In other words, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If frame sync cannot be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window is released immediately. 3-3. Error correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD2510Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. * The correction status can be monitored outside the LSI. See the Table 3-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible C2 correction impossible Table 3-2. - 33 - No C1 errors One C1 error corrected Two C1 errors corrected C1 correction impossible No C2 errors One C2 error corrected Two C2 errors corrected Three C2 errors corrected Four C2 errors corrected No C1 errors One C1 error corrected Description ; C1 pointer reset ; C1 pointer reset -- -- ; C1 pointer set ; C1 pointer set ; C1 pointer set ; C1 pointer set ; C2 pointer reset ; C2 pointer reset ; C2 pointer reset ; C2 pointer reset ; C2 pointer reset -- ; C1 pointer copy ; C2 pointer set CXD2510Q Timing Chart 3-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 3-4. DA Interface * The CXD2510Q has two modes as DA interfaces. a) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. b) 64-bit slot interface This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first. When LRCK is low, the data is for the left channel. - 34 - Timing Chart 3-4 48bit slot Normal-Speed Playback PSSL = L LRCK (44.1K) 6 7 8 9 10 11 12 24 1 2 3 4 5 DA15 (2.12M) WDCK DA16 R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB - 35 - 24 L0 Rch MSB 48bit slot Double-Speed Playback LRCK (88.2K) 12 DA15 (4.23M) WDCK DA16 R0 Lch MSB (15) CXD2510Q Timing Chart 3-5 64 Bit slot Normal Speed PB PSSL = L DA12 (44.1K) 8 9 10 11 12 13 14 15 20 30 31 32 1 2 3 4 5 6 7 DA13 (2.82M) DA14 R ch LSB (0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R15 L ch LSB (0) - 36 - 10 15 20 25 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L ch LSB 64 Bit slot Double- Speed PB DA12 (88.2K) 1 2 3 4 5 DA13 (5.64M) DA14 R ch LSB (0) L15 CXD2510Q CXD2510Q 3-5. Digital Out There are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2510Q supports type 2 form 1. In addition, regarding the clock accuracy of the channel status, level III is set automatically when the crystal clock is used and level II is variable pitch. In addition, Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3). DOUT is output when the crystal is 34MHz, the variable pitch is reset, and DSPB = 1. Therefore, set MD2 to 0 and turn DOUT off. bit 0 to 3 -Sub Q control bits that matched twice with CRCOK Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q 32 48 0 176 bit 0 to 3 - Sub Q control bits that matched twice with CRCOK bit29 - Varipitch: 1 X'Tal: 0 Table 3-6. 3-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and fine search are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but can be sent to the CXD2510Q. In addition, when using the auto sequence, connect the CPU, RF and SSP as shown in Fig. 3-7, and turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). - 37 - CXD2510Q In addition, a MAX timer is built in as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See 1-2, $4X commands concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-8. The auto focus is executed after focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Connection diagram for using the auto sequencer (example) RF MIRR FOK MIRR FOK DATA CXD2510Q CLOK Micro-computer XLAT SENS C. out SSP SENS DATA CLK XLT CNIN SEIN DATO CLKO XLTO Fig. 3-7. - 38 - CXD2510Q Auto focus Focus search up FOK = H YES NO FZC = H YES NO Check whether FZC is continuously high for the period of time E set with register 5. FZC = L YES Focus servo ON NO END Fig. 3-8. (a) Auto Focus Flow Chart $47latch XLAT FOK SEIN (FZC) BUSY Command for SSP $03 Blind E $08 Fig. 3-8. (b) Auto Focus Timing Chart - 39 - CXD2510Q (b) Track jump 1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and sled servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 3-9. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 3-10. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, when 5 tracks have been counted through CNIN, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5), the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 3-11. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or higher. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 3-12. The one difference from a 2N-track jump is that a higher precision is achieved by controlling the traverse speed. The track jump count is set in register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F in register 6 and overflow G in register 5. After N tracks have been counted through CNIN, the brake is applied to the actuator and sled. This is performed by turning the tracking servo for the actuator on, and by kicking the sled in the opposite direction. The cancel command $40 is sent from the CPU when track jump is terminated. Set overflow G to the speed required to slow up just before the track jump terminates. The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump. (Set the target track count N- for the traverse monitor counter which is set in register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset.) - 40 - CXD2510Q 1 Track Track kick sled servo (REV kick for REV jump) WAIT (Blind A) CNIN = NO YES Track REV kick WAIT (Brake B) Track sled servo ON (FWD kick for REV jump) END Fig. 3-9. (a) 1-Track Jump Flow Chart $48 (REV = $49) latch XLAT CNIN BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 3-9. (b) 1-Track Jump Timing Chart - 41 - CXD2510Q 10 Track Track, sled FWD kick WAIT (Blind A) CNIN = 5 ? YES Track, REV kick NO (Counts CNIN x 5) C = Overflow ? YES Track, sled servo ON NO Checks whether the CNIN cycle is longer than overflow C. END Fig. 3-10. (a) 10-Track Jump Flow Chart $4A (REV = $4B) latch XLAT CNIN BUSY Blind A Command for SSP CNIN 5count Overflow C $2A ($2F) $2E ($2B) $25 Fig. 3-10. (b) 10-Track Jump Timing Chart - 42 - CXD2510Q 2N Track Track, sled FWD kick WAIT (Blind A) CNIN (MIRR) = N YES Track REV kick NO Counts CINI for the first 16 times and MIRR for more times. C = Overflow YES Track servo ON NO WAIT (Kick D) Sled servo ON END Fig. 3-11. (a) 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLAT CNIN (MIRR) BUSY Blind A Command $2A ($2F) for SSP CNIN (MIRR) N count $2E ($2B) Overflow $26 ($27) Kick D $25 Fig. 3-11. (b) 2N-Track Jump Timing Chart - 43 - CXD2510Q Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) CNIN = N ? NO YES Track Servo ON Sled REV Kick Track jump is terminated by sending and latching $40 from the CPU. END Fig. 3-12. (a) Fine Search Flow Chart $44 (REV = $45) latch XLAT $40 (cancel) latch CNIN Kick D $26 ($27) Command for SSP Kick F Traverse Speed Control (Overflow G) & CNIN N count $27 ($26) $2A ($2F) $25 Fig. 3-12. (b) Fine Search Timing Chart - 44 - CXD2510Q 3-7. Digital CLV Fig. 3-13 shows the block diagram. Digital CLV makes PWM output in CLVS, CLVP and other modes with the MDS error or MDP error signal sampling frequency increased to 130kHz during normal-speed operation. In addition, the digital spindle servo can set the gain. Digital CLV CLVS U/D MDS Error MDP Error Gain CLVS Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 Mux CLV P Gain MDS Gain DCLV CLV-P/S CLV S Over Sampling Filter-2 Noise Shape KICK, BRAKE STOP Modulation Mode Select MDP DCLVMD CLVS U/D: Up/down signal from the CLV-S servo. MDS error: Frequency error for CLV-P servo. MDP error: Phase error for CLV-P servo. MDS Fig. 3-13. Block Diagram - 45 - CXD2510Q 3-8. Asymmetry Compensation Fig. 3-14 shows the block diagram and circuit example. D2510 28 ASYE ASYO R1 RF 24 R1 27 R2 R1 ASYI 26 R1 25 BIAS R1 2 = R2 5 Fig. 3-14. Example of an Asymmetry Compensation Application Circuit 3-9. Playback Speed In the CXD2510Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin, double-speed command (DSPB), VCO selection command (VCOSEL) and command transfer rate selector (ASHS). Also, the minimum operating voltage changes according to the playback mode. (See the Recommended Operating Conditions.) Playback modes Mode 1 2 3 4 5 6 7 X'tal 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 1 VCOSEL 0/1 0/1 1 1 0/1 0/1 0/1 ASHS 0 0 1 1 0 0 0 Playback speed x1 x2 x2 x4 x1 x2 x1 Error correction C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double However, Fs = 44.1kHz. - 46 - Application Circuit FE TE RF LDON VCC VO VCC MUTE SCOR SQCK SUBQ GFS CLK XLT DATA XRST SENS FOK GND GND VDD LDON SQSO SBSO 64 SCOR WFCK 62 EMPH DOUT MD2 C16M FSOF FSTT XTSL XTAO CXD2510Q XTAI VSS 61 60 59 58 57 56 GND GND 55 54 53 GND 52 APTL 51 APTR MNT0 MNT1 50 49 48 GND MNT2 47 MNT3 XRAOF C2PO RFCK GFS RF 24 GND BIAS ASYI ASYO ASYE NC PSSL XPLCK DATA (48) BCLK (48) DATA (64) BCLK (64) LRCK (64) GTOP XUGF 46 45 44 43 42 41 RFCK GFS XPLCK GND DOUT 63 WFCK EXCK RV1 FE RV2 TE RF GND GND GND SEIN VDD XLAT XLTO CNIN MIRR DATA XRST MIRR CLKO CLOK SENS DATO MUTE SQCK C15 C16 C13 C11 C14 C17 FOK 1 2 3 4 5 DVCC CC1 CC2 FOK EFM CXA1372AQ DFCT MIRR 29 GND 28 27 26 25 18 19 20 GND 21 22 23 CLTV AVDD AVSS PCO FILI FILO 17 VCKI 16 VPCO 15 NC 14 NC DGND SENS COUT XRST DIRC LOCK CLK XLT SL- FSET ISET SSTOP AVCC DATA 13 TEST0 30 DFCT 12 VSS ASY 31 11 PDO 32 10 TEST 33 9 VCOI 34 8 VCOO 35 7 NC 36 6 LOCK MDS MDP MON CP RF0 DVCC RF1 CB FSW FOK 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GND GND TD FD SLD SPD C12 48 47 46 45 44 43 42 41 40 39 38 37 FZC TE TZC ATSC TDFCT GND TRACK-D R1 1 VC GND C9 2 FGD FOCUS-D 3 FS3 GND GND 4 FLB C10 SLED-D 5 FEO GND 6 FE- GND GND GND GND GND C23 C26 8 TGU SL+ SL0 WDCK(48) R5 1M AVDD 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 XUGF GND GND 200p GTOP R9 C35 GND R10 R11 R12 LRCK (48) VDD VSS GND VCC C2PO BCLK DATA MUTE LRCK GND CXD2510Q Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. WDCK DEMP - 47 - R4 R3 SSTOP 9 TG2 GND SPIND-D 7 SRCH FDFCT FE MNT0 MNT1 MNT2 MNT3 GND XRAOF GND 10 AVCC R2 11 TA0 12 TA- GND R7 13 14 15 16 17 18 19 20 21 22 23 24 C28 C27 R6 GND GND GND GND R14 R13 CXD2510Q Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15 65 40 + 0.4 14.0 - 0.1 17.9 0.4 A 80 25 + 0.2 0.1 - 0.05 0.8 0.12 M + 0.15 0.35 - 0.1 + 0.35 2.75 - 0.15 0 to 10 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE QFP080-P-1420-A QFP 80PIN (PLASTIC) 23.9 0.2 20.0 0.2 0.15 0.05 64 65 41 40 14.0 0.2 17.9 0.2 0.8 80 1 0.35 0.1 0.15 M 24 15 25 4 - 1.0 A C1 .2 4 - 0.8 1.45 15 0.8 0.15 0 to 10 DETAIL A EPOXY RESIN SOLDER PLATING 42 ALLOY 1.6g 0.8 0.2 1.95 0.15 1 24 0.24 0.15 + 0.20 2.7 - 0.16 0.15 NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L051 QFP080-P-1420-AH LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT - 48 - 2.94 0.15 15 16.3 15 |
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